[geda-user] opper ring flag for vias and pins

[Bernd Walter]

Because I just remember this, while I wrote about holes and multilayer.
I would love to selectively switch of the copper ring per layer on
vias and pins.
The reason is that I only need to ring on solder side and on connecting
layers.
On layers I don't need the ring it just reduces space, especially
problematic with a via field e.g. inside a BGA.
It is not just routing space - the wider space between vias and pins
are preferable for groundplanes too.

[Dave Curtis]

Post by Bernd Walter
Because I just remember this, while I wrote about holes and multilayer.
I would love to selectively switch of the copper ring per layer on
vias and pins.
The reason is that I only need to ring on solder side and on connecting
layers.
On layers I don't need the ring it just reduces space, especially
problematic with a via field e.g. inside a BGA.
It is not just routing space - the wider space between vias and pins
are preferable for groundplanes too.

So one thing I thought of that might help:
Set the pad diameter on the Pin[] to the small diameter that you want on
the inner layers. Larger pads cans be had on comp and solder side by
drawing coincident Pad[] elements with the same pin number.

[Bernd Walter]

Post by Dave Curtis

Post by Bernd Walter
Because I just remember this, while I wrote about holes and multilayer.
I would love to selectively switch of the copper ring per layer on
vias and pins.
The reason is that I only need to ring on solder side and on connecting
layers.
On layers I don't need the ring it just reduces space, especially
problematic with a via field e.g. inside a BGA.
It is not just routing space - the wider space between vias and pins
are preferable for groundplanes too.

Set the pad diameter on the Pin[] to the small diameter that you want on
the inner layers. Larger pads cans be had on comp and solder side by
drawing coincident Pad[] elements with the same pin number.

This could work as a hack for most cases.
But there are oviously some drawbacks.
You can't have a copper ring in inner layers, but this is ok if you
connect to polygons with full copper contact only.
And by having pads on vias you need to add them to the netlist.

[Peter C.J. Clifton]

Post by Bernd Walter

Post by Dave Curtis

Post by Bernd Walter
Because I just remember this, while I wrote about holes and multilayer.
I would love to selectively switch of the copper ring per layer on
vias and pins.
The reason is that I only need to ring on solder side and on connecting
layers.
On layers I don't need the ring it just reduces space, especially
problematic with a via field e.g. inside a BGA.
It is not just routing space - the wider space between vias and pins
are preferable for groundplanes too.

Set the pad diameter on the Pin[] to the small diameter that you want on
the inner layers. Larger pads cans be had on comp and solder side by
drawing coincident Pad[] elements with the same pin number.

This could work as a hack for most cases.
But there are oviously some drawbacks.

You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

[Dave Curtis]

Post by Peter C.J. Clifton

Post by Bernd Walter

Post by Dave Curtis

Post by Bernd Walter
Because I just remember this, while I wrote about holes and multilayer.
I would love to selectively switch of the copper ring per layer on
vias and pins.
The reason is that I only need to ring on solder side and on connecting
layers.
On layers I don't need the ring it just reduces space, especially
problematic with a via field e.g. inside a BGA.
It is not just routing space - the wider space between vias and pins
are preferable for groundplanes too.

Set the pad diameter on the Pin[] to the small diameter that you want on
the inner layers. Larger pads cans be had on comp and solder side by
drawing coincident Pad[] elements with the same pin number.

This could work as a hack for most cases.
But there are oviously some drawbacks.

You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

How is that handled in other CAD systems? Is "no inner annuli" a part
of the footprint spec, or are they deleted after placing the part?

[DJ Delorie]

Post by Peter C.J. Clifton
You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

Aren't there manufacturability issues if you do that? I.e. voids
where the copper should be, causing breaks in the barrel?

[Bernd Walter]

Post by DJ Delorie

Post by Peter C.J. Clifton
You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

Aren't there manufacturability issues if you do that? I.e. voids
where the copper should be, causing breaks in the barrel?

Why should there be any?
I can't tell for sure, but when the holes are drilled and plated after
stacking then such a plated hole without inside annular rings should
be just the same as they would be with a standard 2-layer board.
But I just investigated some very high densisty CPU boards I had
within reach and all of them used microvias, but had at least rings
on the outside layers of all vias.
I probably should ask a board manufacturer about their opinions.

[Bernd Walter]

Post by Bernd Walter

Post by DJ Delorie

Post by Peter C.J. Clifton
You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

Aren't there manufacturability issues if you do that? I.e. voids
where the copper should be, causing breaks in the barrel?

Why should there be any?
I can't tell for sure, but when the holes are drilled and plated after
stacking then such a plated hole without inside annular rings should
be just the same as they would be with a standard 2-layer board.
But I just investigated some very high densisty CPU boards I had
within reach and all of them used microvias, but had at least rings
on the outside layers of all vias.
I probably should ask a board manufacturer about their opinions.

Just a random manufacturer found by websearch:
http://www.eurocircuits.com/index.php/component/content/article/28-glossary/237-ipi-inner-layer-pad-insulation
They defines spacing requirements for such a non ringed hole independend
if plated or not.
So it should be Ok to have non ringed holes in inner layers at least.

[Peter Clifton]

Post by DJ Delorie

Post by Peter C.J. Clifton
You need to be able to remove inner layer pad annuli completely for
signal integrity reasons on some high-speed lines.

Aren't there manufacturability issues if you do that? I.e. voids
where the copper should be, causing breaks in the barrel?

Apparently not.. I've seen it recommended for a number of high-speed
applications now. I guess the pre-preg resin fills the void? (Or if not
completely - that it does enough for plating to succeed).


--
Peter Clifton <peter.clifton-j0HF+osULJQMjHSeoOxd2MuBeof9RJB+Wmv/***@public.gmane.org>

Clifton Electronics